Dynamic fault-tolerant design for array processors based on immunology

Inspired by the biological immunology principle and using its property of autonomy, learning and memory for reference, this paper focuses on the fault-tolerant design method of array processors which has real-time detection and dynamic configuration capabilities, to improve the chip´s reliability by ensuring that when fault occurs in one or more of processor elements the chip can also work normally. This paper discusses the heterogeneous features of array processors, the structure of resource node and communication node. Research the fault-tolerance strategy of array processor, and the immune response mechanism of array processor, to achieve the real-time immune process of perception, training, response and feedback. This paper focuses on researching the structure and the algorithm of router switch unit with 90 mm technology which has the dynamic fault-tolerant function. It has the guiding significance on R & D of array processors for industry circles.