Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization

Process-induced mechanical stress is used to enhance carrier mobility and drive current in contemporary CMOS technologies. Stressed cells have reduced delay but larger leakage consumption. Its efficient power/delay trading ratio makes mechanical stress an enticing alternative to other power optimization techniques. This paper proposes an effective urgentpath guided approach that improves dual V_t technique by incorporating gate sizing and mechanical stress simultaneously. The introduction of mechanical stress is shown to achieve 9.8% leakage and 2.8% total power savings over combined gate sizing and dual V_t approach.