Interconnects for submicron ASICs

It is suggested that the ULSI application-specific integrated circuit (ASIC) requirements of high performance and density can be met with a high-conductivity multilevel interconnect. The proposed interconnect system will utilize salicide and local interconnect technology to reduce device parasitics and a novel metal structure to improve reliability. The metal levels consist of layered conductors composed of antireflection material on top and barrier material on the bottom of the Al-Cu conductor. Planarization is a must for each level of interconnects as well as contact and via fill such as selective tungsten or blanket tungsten deposition and etch back. It is imperative to determine a metal structure that is compatible with the overall multilevel interconnect process flow and is capable of meeting the reliability requirements of the interconnects. Innovations will also be needed in the new interconnect structure to provide coincident contacts and vias to meet the stringent requirements of submicron ASIC applications