Board level thermal reliability modeling of POP assembling

A thermal reliability model is proposed for board level package-on-package (POP) assembling in this work, Design analysis is performed to study the effect of key package parameters such as die size, substrate size, solder ball size, etc. According to the finite elements analysis on the thermal reliability model, thermal distribution and thermal gratitude of the 3-dimension package is obtained within ±10% error limit. Therefore, the live of working chip can be predicted by the thermal distribution, and the thermal stress of key point can be concluded by the thermal gratitude. The valid model is implemented in a 3-package stacked structure, by comparing the influence of the different stacked sequence of the stacked package, an optimized process plan of the package-on-package assembling can be given at last.