Design of a low power 12-bit ADC

This paper presents a 1 V, 12 bit two-step Analog to digital converter (ADC) architecture based on the dichotomic anticipation algorithm. It proposes a comparator and operational amplifier blocks with reduced area, power consumption, and input capacitance. We have designed a 6-bit ADC to be embedded as a coarse converter in 8-bits ADC based on the “Flash” Principle. An ADC of 12-bits has been designed and simulated. Static parameters such as INL and DNL are determined and presented. Simulation results show that this proposed 12-bit ADC consumes about 6.45 mW with 1 V supply voltage, for 850-mV input signal in 0.35 μm CMOS technology. The chip area occupies less than 4mm².