DocumentCode :
2683376
Title :
CIG: A CAD tool for IP integration in SoC design
Author :
Abbes, Fatma ; Benamor, Nader ; Abid, Mohamed ; Yanguy, Amira
Author_Institution :
CES Lab., ENIS Eng. Sch., Sfax, Tunisia
fYear :
2010
fDate :
23-25 March 2010
Firstpage :
1
Lastpage :
4
Abstract :
Actually, SoC design is based on the reuse of Intellectual Property (IP). Designer´s attempts such as flexibility, cost constraints, high performance and time to market can thus be helpfully managed. However, the correct integration of the generated architectures/components in a design implies complex verification and design problems. Since IPs are heterogeneous, the design of communication interfaces between them is more and more difficult. In this paper, we present a CIG: Communication Interface Generator; a CAD tool automating the integration process of hardware accelerators/ coprocessors aiming data flow emerged systems.
Keywords :
CAD; coprocessors; data flow analysis; logic design; peripheral interfaces; system-on-chip; CAD tool; IP integration; SoC design; communication interface generator; complex verification; coprocessor; data flow emerged system; design problem; hardware accelerator; integration process; intellectual property; Computer interfaces; Costs; Design automation; Design engineering; Design methodology; Educational institutions; Hardware; Intellectual property; Laboratories; Protocols;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on
Conference_Location :
Hammamet
Print_ISBN :
978-1-4244-6338-1
Type :
conf
DOI :
10.1109/DTIS.2010.5487577
Filename :
5487577
Link To Document :
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