Modeling SW to HW task migration for MPSOC performance analysis

Author

Bennour, Imed ; Sebai, Dorsaf ; Jemai, Abderrazak

Author_Institution

EμE Lab., Fac. of Sci. at Monastir, Monastir, Tunisia

fYear

2010

fDate

23-25 March 2010

Firstpage

1

Lastpage

6

Abstract

Codesign choices of a system differ in terms of different hardware/software partitions, different types of architectural components, different communication architectures, etc. This paper presents an analytic method to estimate the gain on a system throughput when a software task is selected to be moved to hardware during the codesign process. The method is based on formal transformations of a Synchronous Data Flow Graph that models the application as well as its mapping to architecture. The proposed method is applied to the MJPEG decoder using the predictable MPSOC design tool SDF³.

Keywords

data flow graphs; hardware-software codesign; multiprocessing systems; system-on-chip; MPSOC performance analysis; SW to HW task migration; architectural components; codesign choices; codesign process; communication architectures; hardware/software partitions; software task; synchronous data flow graph; Analytical models; Computer architecture; Decoding; Equations; Flow graphs; Hardware; Laboratories; Mathematical model; Performance analysis; Throughput; MPSOC; SW to HW task migration; Synchronous DataFlow; performance estimation; predictable design flow;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on

Conference_Location

Hammamet

Print_ISBN

978-1-4244-6338-1

Type

conf

DOI

10.1109/DTIS.2010.5487581

Filename

5487581