Multi-Radio Support on Asynchronous Processor Cores: A Design Methodology Approach for Cognitive Radios

It has only been very recently that commercial asynchronous processors on FPGAs have started to take shape, and much of the design details of the architecture prototypes are not publicly available. Programming description languages and CAD tools for asynchronous design are still maturing, and there are different languages like CSP, Tangram, OCCAM, Verilog+, etc., which are difficult to port to different asynchronous target architectures. The on-going research on multi-radio realization on asynchronous microprocessors (that do not run an operating system) focuses on a custom-instruction based hybrid optimality structure involving a combination of STAPL (single track handshake asynchronous pulse logic) circuits and QDI (quasi-delay insensitive) circuits design styles which are fundamentally different in implementation character. Compiling different description languages dynamically run-time on reconfigurable asynchronous targets where the target architectures might themselves morph based on the processed data (an embodiment of multimedia information systems for ultra-low power and battery conserving constrains), is currently difficult to realize in an optimal manner. This work-in-progress paper attempts to describe a design proposal that extends the Microsoft Phoenix compiler framework to include asynchronous instruction set targets and aims at extending the functionality of asynchronous processors to support mobile computing and development of future multimedia information systems.