Title :
An IC for turbo-codes encoding and decoding
Author :
Berrou, C. ; Combelles, P. ; Penard, P. ; Talibart, B.
Author_Institution :
ENST de Bretagne, Brest, France
Abstract :
A turbo-code is the parallel concatenation of two recursive systematic convolutional codes separated by a non-uniform interleaving. The decoding process is iterative and error-correcting capacity increases with the number of iterations. The coding memory of 2 identical recursive systematic coders is 4 b long and their polynomials are 23,35. The decoding module is made up of 2 soft-output Viterbi algorithm decoders, interleaving and de-interleaving modules, some delay lines, and a synchronization block that also features supervision functions.
Keywords :
CMOS logic circuits; Viterbi decoding; concatenated codes; convolutional codes; error correction codes; interleaved codes; 0.8 mum; 2-metal CMOS technology; IC; coding memory; delay lines; error-correcting capacity; interleaving modules; iterative decoding; nonuniform interleaving; parallel concatenation; recursive systematic convolutional codes; soft-output Viterbi algorithm decoders; supervision functions; synchronization block; turbo-code decoding; turbo-code encoding; Circuits; Convolutional codes; Encoding; Interleaved codes; Iterative decoding; Maximum likelihood decoding; Redundancy; Registers; Turbo codes; Viterbi algorithm;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535444
