• DocumentCode
    2685388
  • Title

    High density 3D integration

  • Author

    Yu, Roy

  • Author_Institution
    IBM T.J. Watson Res. Center, Yorktown Heights, NY
  • fYear
    2008
  • fDate
    28-31 July 2008
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    This paper discusses the current and future needs in continued CMOS scaling, reviews the status of the transfer and joining (TJ) technology for MCM-D and wafer level 3DI integration, and explores the opportunities of the TJ technology in the realm of the ldquoMore than Moorerdquo era.
  • Keywords
    CMOS integrated circuits; CMOS scaling; high density integration; three-dimensional integration; transfer-and-joining technology; wafer level integration; CMOS technology; Central Processing Unit; Computer architecture; Costs; Delay; Energy consumption; Hybrid integrated circuits; System performance; Transistors; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-2739-0
  • Electronic_ISBN
    978-1-4244-2740-6
  • Type

    conf

  • DOI
    10.1109/ICEPT.2008.4606934
  • Filename
    4606934
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2685388