Jitter in deep submicron CMOS single-ended ring oscillators

A 1/f³ phase noise corner frequency of approximately 1 MHz has been observed in phase noise measurements of single-ended ring oscillators in a 0.18μm CMOS process. Consequently, increased loop bandwidth is necessary for PLLs in a deep submicron CMOS process to minimize jitter contributed by the VCO. As a guide to design, the time domain figure-of-merit κ is measured as a function of channel width, length, and inverter stage delay.