• DocumentCode
    2685930
  • Title

    Jitter in deep submicron CMOS single-ended ring oscillators

  • Author

    Chengxin Liu ; McNeill, John A.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA
  • Volume
    2
  • fYear
    2003
  • fDate
    21-24 Oct. 2003
  • Firstpage
    715
  • Abstract
    A 1/f3 phase noise corner frequency of approximately 1 MHz has been observed in phase noise measurements of single-ended ring oscillators in a 0.18μm CMOS process. Consequently, increased loop bandwidth is necessary for PLLs in a deep submicron CMOS process to minimize jitter contributed by the VCO. As a guide to design, the time domain figure-of-merit κ is measured as a function of channel width, length, and inverter stage delay.
  • Keywords
    1/f noise; integrated circuit noise; jitter; oscillators; phase noise; 0.18 microns; PLL; VCO; channel length function; channel width function; deep submicron CMOS; figure-of-merit; inverter stage delay; jitter minimization; loop bandwidth; phase noise measurements; single-ended ring oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2003. Proceedings. 5th International Conference on
  • ISSN
    1523-553X
  • Print_ISBN
    0-7803-7889-X
  • Type

    conf

  • DOI
    10.1109/ICASIC.2003.1277310
  • Filename
    1277310
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2685930