Optimization of CAVLC algorithm and its FPGA implementation

As a new generation of video frequency coding standard, H.264/AVC is excellent in compression performance, while its complexity is much higher than common encoder. Based on the detailed analysis of CAVLC algorithm, this paper first points out the ldquobottleneckrdquo of CAVLC encoder implementation, then presents the optimization scheme for the major modules of CAVLC encoder, which includes VLC table prediction with multiple reference blocks, fast look-up table matching, and arithmetic eliminating method etc. It is successfully synthesized and simulated with EDA tools and implemented in FPGA of Cyclone II EP2C20F484, and the speed of the coding module is up to 165 MHz. The experimental results show that the improved design scheme will be helpful to achieve the real-time processing purpose by saving the hardware resource together with the increasing coding rate.