Title :
A 250 MHz clock for SOC systems
Author :
Chen Jia ; Boan Liu
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
This paper introduces a method to implement a phase-locked loop (PLL) based on ring oscillator. In order to reject the jitters, a voltage regulator is applied to reduce the power-supply noise, which is the most common and dominant source of jitter. The simulation result shows that the voltage regulator can achieve a power-supply rejection ratio (PSRR) greater than 50dB while VCO operating at frequencies about 1 GHz. And it is in layout. The system is integrated in a 0.25-μm 2-poly 5-metal digital CMOS technology.
Keywords :
clocks; integrated circuit noise; jitter; phase locked loops; power supply circuits; system-on-chip; voltage regulators; voltage-controlled oscillators; 0.25 microns; 250 MHz; CMOS technology; PLL; SOC systems; clock; phase-locked loop; power supply noise; power-supply rejection ratio; ring oscillator; voltage-controlled regulator;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277312
