Title :
A fully symmetrical PFD for fast locking low jitter PLL
Author :
Yong-Ming Li ; Hong-yi Chen
Abstract :
A fully symmetrical phase-frequency detector (fs-PFD) is proposed in this paper. Because there is no feedback path in the fs-PDF circuit, it can be operated above 1GHz. Some improvements are made to get a dead zone of only 12 ps. Phase locked loop (PLL) using the fs-PFD has a reduced locking time and an output signal frequency with little jitter.
Keywords :
jitter; phase detectors; phase locked loops; circuit feedback; dead zone; fast locking PLL; feedback path; fully symmetrical PFD; fully symmetrical phase-frequency detector; low jitter PLL; output signal frequency; phase locked loop; reduced locking time;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277313
