DocumentCode
2686021
Title
The programmable logic implementation of GPS/GLONASS clock synchronization
Author
Liu Chunping
Author_Institution
Sch. of Eng. & Technol., Shenzhen Univ., China
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
732
Abstract
A GPS/GLONASS clock synchronization implementation based on programmable logic is presented. The GPS/GLONASS PPS (standard 1 second signal) is regarded as a reference of the whole clock synchronization system that consists of two levels PLL. Both the GPS/GLONASS PPS and OCXO assure the long-term stability and short-term stability of clock signals. All the digital circuit, including digital phase error discriminator, 2S-generating module, phase error detecting and controlling module, can be built in a programmable logic chip.
Keywords
Global Positioning System; clocks; digital circuits; phase locked loops; programmable logic devices; synchronisation; 2S-generating module; GLONASS; GPS; OCXO; PLL; PPS; circuit stability; clock signals; clock synchronization; digital circuit; digital phase error discriminato; phase error control; phase error detecting; programmable logic chip;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277315
Filename
1277315
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