The design and FPGA realization of the long PN code acquisition circuit based on digital matched-filter

In a low-earth orbit (LEO) satellite system the received signal is characterized by low signal to noise, it requires a minimum spreading processing gain of 30dB, i.e., the pseudonoise (PN) code length is 1023. However, the application specific integrated circuit (ASIC) based on digital matched-filter (DMF) for PN code acquisition on the market can´t support such a long PN code length. It is necessary to use field programmable gate array (FPGA) to design the long PN code acquisition circuit based on DMF for the so high spreading processing gain. In this paper, the PN code acquisition circuit based on DMF is analyzed. A new approach to PN code acquisition based on DMF, which can obtain high spread processing gain (30dB) while the cost of the hardware is largely depressed, is presented. VHDL design, verification and FPGA realization of the DMF is accomplished, and main design results are also given.