DocumentCode
2686122
Title
Logarithmic complexity implementation for leading zeros detector
Author
Wei He ; Haiping Sun ; Jinqing Cai ; Minglun Gao
Author_Institution
Inst. of VLSI Design, Hefei Univ. of Technol., Anhui, China
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
761
Abstract
A logarithmic complexity implementation for the leading zeros detector is presented. The relation between the leading zeros detection result and the input string to be detected is analyzed, and then the logarithmic complexity algorithm is inferred, which takes the advantage of both speed and area. The complexities of the algorithm in terms of time and hardware are given. The experimental results of several concrete schemes based on the logarithmic complexity algorithm are also discussed.
Keywords
adders; floating point arithmetic; logic design; algorithm complexities; leading zeros detector; logarithmic complexity algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277322
Filename
1277322
Link To Document