DocumentCode
2686135
Title
Clock-buffer-chip with multiple-target automatic skew compensation
Author
Watson, R.B., Jr. ; Iknaian, R.B.
Author_Institution
Digital Equipment Corp., USA
fYear
1995
fDate
15-17 Feb. 1995
Firstpage
106
Lastpage
107
Abstract
A clock chip accurately delivers low skew (/spl sim/1 ns) clock to the internals of multiple ASICs, correcting for its own process variations as well as remotely correcting for variations in both ASIC clock buffer delay and in module etch electrical length.
Keywords
application specific integrated circuits; buffer circuits; clocks; compensation; 1 ns; clock-buffer-chip; delay; module etch electrical length; multiple ASICs; multiple-target automatic skew compensation; Application specific integrated circuits; Clocks; Delay lines; Etching; Flip-flops; Propagation delay; Regulators; Semiconductor process modeling; Stress; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-2495-1
Type
conf
DOI
10.1109/ISSCC.1995.535450
Filename
535450
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