DocumentCode :
2686140
Title :
Combined selection of tile sizes and unroll factors using iterative compilation
Author :
Kisuki, T. ; Knijnenburg, P.M.W. ; Boyle, M. F P O
Author_Institution :
KIACS, Leiden Univ., Netherlands
fYear :
2000
fDate :
2000
Firstpage :
237
Lastpage :
246
Abstract :
Loop tiling and unrolling are two important program transformations to exploit locality and expose instruction level parallelism, respectively. In this paper, we address the problem of how to select tile sizes and unroll factors simultaneously. We approach this problem in an architecturally adaptive manner by means of iterative compilation, where we generate many versions of a program and decide upon the best by actually executing them and measuring their execution time. We evaluate several iterative strategies. We compare the levels of optimization obtained by iterative compilation to several well-known static techniques and show that we outperform each of them on a range of benchmarks across a variety of architectures. Finally, we show how to quantitatively trade-off the number of profiles needed and the level of optimization that can be reached
Keywords :
optimising compilers; parallel architectures; instruction level parallelism; iterative compilation; loop tiling; unrolling; Cost function; Embedded system; Hardware; Iterative methods; Modems; Optimizing compilers; Predictive models; Tiles; Time measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques, 2000. Proceedings. International Conference on
Conference_Location :
Philadelphia, PA
ISSN :
1089-795X
Print_ISBN :
0-7695-0622-4
Type :
conf
DOI :
10.1109/PACT.2000.888348
Filename :
888348
Link To Document :
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