Tracking radar digital matched-filter ASIC design and its error analysis

Author

Liu Zhenyu

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

Volume

2

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

777

Abstract

Matched-filter is widely used in real time signal processing, especially in radar signal processing. This paper presents a novel structure of digital tracking radar matched-filter, whose hardware overhead is one third of traditional design but its throughput is doubled. With block-floating-point arithmetic, the precision is high improved. The whole digital matched-filter is implemented in just one chip of FPGA. This ASIC has two work modes: 512 points pulse compression and 256 points pulse compression. It complements three channels of 512-points complex signal in 102us. The noise-to-signal ratio formula of this matched-filter is deduced at the end of the paper.

Keywords

application specific integrated circuits; digital filters; floating point arithmetic; integrated circuit design; matched filters; radar signal processing; radar tracking; 102E-6 s; ASIC design; FFT; FPGA; block-floating-point arithmetic; digital matched-filter; digital tracking radar matched-filter; error analysis; fast Fourier transform; hardware overhead; pulse compression; radar signal processing; real time signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277326

Filename

1277326