DocumentCode :
2686232
Title :
Efficient backtracking instruction schedulers
Author :
Abraham, Santosh G. ; Meleis, Waleed M. ; Baev, Ivan D.
Author_Institution :
Hewlett-Packard Co., Palo Alto, CA, USA
fYear :
2000
fDate :
2000
Firstpage :
301
Lastpage :
308
Abstract :
Current schedulers for acyclic regions schedule operations in dependence order and never undo a scheduling decision. In contrast, backtracking schedulers may unschedule operations and can often generate better schedules. In this paper, we describe a conventional cycle schedule, followed by two novel backtracking schedulers, OperBT and ListBT. The full-backtracking OperBT scheduler enables backtracking for all operations and unschedules operations to make space for the current operation. The OperBT scheduler increases the percentage of super-blocks scheduled optimally over a conventional non-backtracking scheduler from an average of 66.9% to 81.4%, an increase of 21.7%. The selective backtracking ListBT scheduler enables backtracking only when scheduling operations for which backtracking is likely to be advantageous. This hybrid scheduler is almost as good as the OperBT backtracking scheduler in terms of generated code quality, but backtracks about four times less often
Keywords :
backtracking; processor scheduling; program compilers; ListBT; OperBT; backtracking instruction schedulers; backtracking schedulers; Arithmetic; Delay; Hybrid power systems; Laboratories; Parallel processing; Pipelines; Process design; Processor scheduling; Registers; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques, 2000. Proceedings. International Conference on
Conference_Location :
Philadelphia, PA
ISSN :
1089-795X
Print_ISBN :
0-7695-0622-4
Type :
conf
DOI :
10.1109/PACT.2000.888354
Filename :
888354
Link To Document :
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