Title :
A 2.4 GOPS data-driven reconfigurable multiprocessor IC for DSP
Author :
Yeung, A.K. ; Rabaey, J.M.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Existing hardware prototyping platforms, often based on commercial processors or FPGAs, cannot cope with the high computation requirements of complex DSP algorithms, especially those with high sampling rate and heterogeneous data-now patterns. The multiprocessor IC presented here is designed to handle these types of algorithms. The chip presented here contains 48 16 b PEs interconnected by a 2-level high bandwidth communication network.
Keywords :
reconfigurable architectures; 16 bit; DSP; computation requirements; data-driven reconfigurable multiprocessor IC; heterogeneous data-now patterns; high bandwidth communication network; processing elements; sampling rate; Bandwidth; Broadcasting; Communication networks; Communication switching; Computer architecture; Data buses; Digital signal processing; Hardware; Prototypes; Switches;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535451
