DocumentCode
2686344
Title
Design of an asynchronous ACS for Viterbi decoder
Author
Wang Jin ; Qiu Yulin ; Hei Yong
Author_Institution
Microelectron. R&D Center, Chinese Acad. of Sci., Beijing, China
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
820
Abstract
In this paper, we present a new asynchronous ACS (adder-compare-select) unit, which is a key building block in the Viterbi decoder. Asynchronous self-timed control and DCVSL (Differential Cascade Voltage Switch Logic) have been used in the ACS unit. The simulation results show that the average case response time 3.51ns is only 42.6% the worst case response time 8.23ns. This explains that the asynchronous ACS unit has performance advantage over the synchronous one.
Keywords
Viterbi decoding; asynchronous circuits; logic design; 3.51 ns; 8.23 ns; DCVSL; Viterbi decoder; adder-compare-select unit; asynchronous ACS; asynchronous self-timed control; differential cascade voltage switch logic;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277336
Filename
1277336
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