Title :
VLSI design of Reed-Solomon decoder based on new architecture of modified Euclidean algorithm
Author :
Xiaoyang Zeng ; Zhenyu Gu ; Chao Chen ; Qianling Zhang
Author_Institution :
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
Abstract :
A RS(255, 223) decoder based on modified Euclidean (mE) algorithm is implemented. A new VLSI architecture of the error-locator and error-evaluator module for mE algorithm is studied. The new architecture can reduce the complexity of the module and the error-probability of the decoder is cut-down also. The RS decoder is implemented using 0.35 μm CMOS technology, and the chip-area is about 30,000 gates, system clock is 65MHz, throughout is about 500Mbits/s. The decoder has the merits of low latency, low complexity and moderate throughput of data.
Keywords :
CMOS digital integrated circuits; Reed-Solomon codes; VLSI; decoding; integrated circuit design; 0.35 microns; 500 Mbit/s; 65 MHz; CMOS technology; Euclidean algorithm; RS 223; RS 255; RS decoder; Reed-Solomon decoder; VLSI design; data throughput; error-evaluator module; error-locator module; error-probability minimization; mE algorithm;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277340
