DocumentCode
2686474
Title
USB3.1 silicon and channel design optimization using artificial neural network modeling
Author
Mo Liu ; Tsai, Jennifer Hsiao-Ping
Author_Institution
Platform Eng. Group, Intel Corp., Santa Clara, CA, USA
fYear
2015
fDate
15-21 March 2015
Firstpage
289
Lastpage
293
Abstract
This paper adopts neural network modeling for USB3.1 Gen 2 high speed signal channel simulation instead of conventional response surface methodology. The paper demonstrates the co-design and optimization flow of USB3.1 silicon and channel parameters and how neural network modeling captures the complex response in a wide range with high accuracy.
Keywords
neural nets; signal processing; USB3.1 silicon; artificial neural network modeling; channel design optimization; channel parameters; high speed signal channel simulation; response surface methodology; Biological neural networks; Fitting; Impedance; Indexes; Neurons; Silicon; Training; Continuous Time Linear Equalizer (CTLE); USB; design of experiment (DOE); neural network; response surface methodology (RSM);
fLanguage
English
Publisher
ieee
Conference_Titel
Electromagnetic Compatibility and Signal Integrity, 2015 IEEE Symposium on
Conference_Location
Santa Clara, CA
Print_ISBN
978-1-4799-1992-5
Type
conf
DOI
10.1109/EMCSI.2015.7107701
Filename
7107701
Link To Document