Title :
A parallel FSM design method and its application in ten gigabit Ethernet access chip
Author :
Zhao Liu ; Lieguang Zeng
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Abstract :
The data flow rate in ten gigabit Ethernet access chip is so high that the chip uses a 64-bit data channel. But the interface between the host and the access chip is 32-bit in width. So the chip needs a parallel interface and a parallel FSM that controls the interface. This paper presents a block diagram for the ten gigabit Ethernet access system and a solution for the parallel FSM design problem.
Keywords :
finite state machines; local area networks; microprocessor chips; parallel architectures; 10 Gbit/s; 32 bits; 64 bits; block diagram; data channel; data flow rate; finite state machines; gigabit Ethernet access system; parallel FSM design method; parallel interface; ten gigabit Ethernet access chip;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277348
