A sea-of-gates FPGA

Author

Goetting, E. ; Schultz, D. ; Parlour, D. ; Frake, S. ; Carpenter, R. ; Abellera, C. ; Leone, B. ; Marquez, D. ; Palczewski, M. ; Wolsheimer, E. ; Hart, M. ; Look, K. ; Voogel, M. ; West, G. ; Tong, V. ; Chang, A. ; Chung, D. ; Hsieh, W. ; Farrell, L. ; Ca

Author_Institution

XILINX Inc., San Jose, CA, USA

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

110

Lastpage

111

Abstract

This CMOS FPGA has programmable interconnect vertically stacked above the logic cells, allowing 2-fold reduction in silicon area while maintaining mutability. This FPGA logic architecture is designed to efficiently implement HDL code, an increasingly important attribute as synthesis tools become prevalent in design entry. To derive an equivalent sea-of-gates gate array (SOG-GA) capacity for the device, parallel-synthesis is employed, with HDL designs synthesized in both the FPGA and gate array.

Keywords

CMOS logic circuits; field programmable gate arrays; hardware description languages; integrated circuit interconnections; CMOS; HDL code; SOG-GA capacity; logic architecture; mutability; parallel-synthesis; programmable interconnect; sea-of-gates FPGA; vertical stack; Capacitance; Delay; Field programmable gate arrays; Implants; Logic programming; MOSFETs; Radio access networks; Routing; Solid state circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535452

Filename

535452