Title :
Integrated power supply packaging technique with reduced parasitic inductance for on-die voltage regulator design and application
Author :
Boping Wu ; Shaowu Huang
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
On-die voltage regulator can improve load regulation, facilitate power management, reduce crosstalk, eliminate transient spikes, and save the board space as well as interconnect pin-counts. This paper presents an integrated circuit package design that provides a low inductance power supply with the capacitive stabilizer for an on-die voltage regulator. A novel 3D design using layered inter-digitated structure is composed of inter-leaved power and ground tracks configured to introduce the negative mutual inductive coupling in between. This design leads to significant reduction of the total parasitic loop inductance, which is verified by electromagnetic simulation using Ansys Q3D. The voltage drop simulated by Spice models is also greatly improved using the proposed layered inter-digitated structure.
Keywords :
integrated circuit design; integrated circuit noise; integrated circuit packaging; three-dimensional integrated circuits; voltage regulators; 3D design; board space reduction; capacitive stabilizer; crosstalk reduction; integrated circuit package design; integrated power supply packaging technique; interconnect pin-count reduction; layered interdigitated structure; load regulation; low inductance power supply; on-die voltage regulator design; parasitic inductance reduction; power management; transient spike elimination; Capacitors; Inductance; Ports (Computers); Power supplies; Regulators; Routing; Voltage control;
Conference_Titel :
Electromagnetic Compatibility and Signal Integrity, 2015 IEEE Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-1992-5
DOI :
10.1109/EMCSI.2015.7107711
