Implementation of DVB demultiplexer system with system-on-a-programmable-chip FPGA

In order to satisfy different application requirements, DVB demultiplexer chip needs a flexible architecture to easily add or remove functional components. In this paper, MPEG-2 protocol related to demultiplexing is analyzed and implemented mainly with one FPGA (APEX 20K400E) based on a system-on-a-programmable chip (SOPC) architecture. The components include but not limit to PID filter, TS demultiplexer, tuner controller and IP parser. Their interfaces connected with on-chip bus are specified by Altera Avalon protocol, which is compatible with Nios CPU. We briefly introduce the demultiplexer system´s hardware architecture, working process and designing considerations to reach the fullest potential of FPGA. The experimental results show that the proposed scheme can provide us flexibility and shorter time-to-market.