A 150 MIPS/W CMOS RISC processor for PDA applications

Author

Nagamatsu, M. ; Tago, H. ; Mijamori, T. ; Kamata, M. ; Murakami, H. ; Ootaguro, Y. ; Goto, H. ; Utsumi, T. ; Teruyama, T. ; Mabuchi, K. ; Kawasumi, A. ; Malik, K.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

114

Lastpage

115

Abstract

This CMOS microprocessor has performance of about 45MIPS at 50 MHz with about 300 mW power dissipation at 3.3 V power supply. It implements about 440 k transistors in a 25 mm/sup 2/ die fabricated by 0.41 /spl mu/m double metal CMOS. It is designed as a core processor for PDA applications, that require high speed graphical operation and digital signal processing functions as well as low power consumption from portability requirements.

Keywords

CMOS digital integrated circuits; 0.4 micron; 3.3 V; 300 mW; 45 MIPS; 50 MHz; CMOS; PDA applications; RISC processor; core processor; digital signal processing functions; double metal CMOS; high speed graphical operation; personal digital assistant; portability requirements; power consumption; power dissipation; CMOS process; Circuit simulation; DH-HEMTs; Digital signal processing; Energy consumption; Ground penetrating radar; Modems; Reduced instruction set computing; Registers; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535454

Filename

535454