Efficient extraction of the interconnect inductances for VLSI design

The effects of on-chip inductances have become increasingly significant with the increasing clock frequencies. We present an efficient approach for extracting inductances on VLSI interconnects by applying approximation formulae. The equations are mapped according to he geometric structures for which they are most suitable in minimizing the runtime of inductance calculation while retaining the required accuracy. Results of a comprehensive evaluation, they were within several percent of the values obtained by using three-dimensional (3-D) field solvers. The efficiency of the proposed approach is also demonstrated by extraction from a real layout design.