A 3.125-Gb/s CMOS transmitter for serial data communications

Author

Wen-Hu Zhao ; Zhi-Gong Wang ; Zhen Shen ; Wei Wu ; En Zhu

Author_Institution

Southeast Univ., Nanjing, China

Volume

2

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

1033

Abstract

A transmitter operating at half the clock frequency of the transmission data rate has been designed with a 0.25μm CMOS technology. It includes a 10:1 multiplexer to serialize 10-bit wide parallel signals to a 3.125Gb/s data stream and a frequency synthesis PLL to generate clock signals for the multiplexer. To verify the design ideas, some of the key components of multiplexer and PLL were fabricated in 0.25μm CMOS process. Tested on wafer, these chips operate stably and obtain the prospective results. The simulation and experiment results demonstrate the transmitter is suitable for high-speed applications and consumes relatively low power dissipation.

Keywords

CMOS integrated circuits; data communication; frequency synthesizers; high-speed integrated circuits; integrated circuit design; low-power electronics; multiplexing equipment; phase locked loops; transmitters; 0.25 microns; 3.125 Gbit/s; CMOS process; CMOS technology; CMOS transmitter; clock signals; frequency synthesis PLL; high-speed applications; low power dissipation; multiplexer; phase locked loop; serial data communications; transmission data rate; wide parallel signals;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277388

Filename

1277388