Title :
New design of RF interface circuits for PICC complying with ISO/IEC14443-2 type B
Abstract :
This paper demonstrates a new set of RF circuits design proposal for PICC complying with ISO/IEC 14443-2 Type B, expatiates on the topology of typical modules and addresses its advantage over former design. The simulation data by Hspice, with the corresponding test of this chip is also given in the following thesis. The design has been implemented upon 0.8 μm CMOS technology successfully. The packaged chip can operate at 13.56MHz with data rate of 106 kbps, hence its feasibility is verified.
Keywords :
CMOS integrated circuits; IEC standards; ISO standards; circuit simulation; integrated circuit design; radiofrequency integrated circuits; smart cards; 0.8 microns; 106 kbit/s; 13.56 MHz; CMOS technology; IEC14443-2 type B; ISO standard; PICC; RF circuits design; RF interface circuits; RFID; demodulation; full wave rectifier; modulation; packaged chip; power-on-off reset; proximity IC card;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277389
