Title :
A 3.3V 50MHz synchronous 16Mb flash memory
Author :
Mills, D. ; Bauer, M. ; Bashir, Adil ; Fackenthal, R. ; Frary, K. ; Gullard, T. ; Haid, C. ; Javanifard, J. ; Kwong, P. ; Leak, D. ; Pudar, S. ; Rashid, Md. Mamunur ; Rozman, R. ; Sambandan, S. ; Sweha, S. ; Tsang, J.
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
A 3.3 V 50 MHz synchronous 16 Mb flash memory serves applications where zero-wait-state direct execution is essential in removing the performance bottleneck attributed to slow memory in performance (/spl ges/25 MHz) systems. This 16 Mb flash chip supports continuous burst cycles for code execution, eliminating costly code shadowing from slow nonvolatile memory to DRAM, resulting in improved system performance and lower cost. Architecture and circuit innovations give 20 ns continuous burst and a maximum data transfer rate of 100 MB/s, resulting in a greater than 3/spl times/ performance improvement over previous 16 Mb devices.
Keywords :
EPROM; 100 MB/s; 16 Mbit; 20 ns; 3.3 V; 50 MHz; circuit architecture; code execution; continuous burst cycles; data transfer rate; synchronous flash memory; zero-wait-state direct execution; Circuits; Clocks; Decoding; Delay; Flash memory; Latches; Nonvolatile memory; Pulse amplifiers; Shadow mapping; System performance;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535456
