Title :
A 6 nsec CMOS EPLD with μW standby power
Author :
Allen, Michael J.
Abstract :
A description is presented of a 28-pin CMOS EPROM (erasable programmable read-only memory)-based programmable logic device optimized for memory-address-decoding applications. A novel architecture provides high-speed operation at CMOS power levels. Reprogrammability and 100% testability of EPROM technology are added benefits. Active power is less than 25% of slower bipolar solutions, and die area is 74 mil2
Keywords :
CMOS integrated circuits; EPROM; cellular arrays; decoding; logic arrays; 28-pin; 6 ns; CMOS EPLD; CMOS power levels; EPROM; architecture; erasable programmable read-only memory; high-speed operation; memory-address-decoding applications; microwatt standby power; programmable logic device; reprogrammability; testability;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56689
