DocumentCode
2687604
Title
Implementation of a BIST scheme for ADC test
Author
Rao Jin ; Ren Ailing ; Ling Ming
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
1128
Abstract
In this paper, we presented algorithms for testing gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC), and proposed an easily integrated built-in-self-test (BIST) scheme on chip, which has been designed using TSMC 0.25μm technology. The experimental results show that the proposed BIST scheme has low area overhead, low test cost and high test accuracy.
Keywords
analogue-digital conversion; built-in self test; integrated circuit testing; 0.25 microns; ADC test; BIST scheme; DNL; INL; TSMC; analog-to-digital converters; differential nonlinearity; gain error; integral nonlinearity; integrated built-in-self-test; test algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277412
Filename
1277412
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