A 3.3 V high-density AND flash memory with 1 ms/512B erase and program time

Author

Nozoe, A. ; Yamazaki, T. ; Sato, H. ; Kotani, H. ; Kubono, S. ; Manita, K. ; Tanaka, T. ; Kawahara, T. ; Kato, M. ; Kimura, K. ; Kume, H. ; Hori, R. ; Nishimoto, T. ; Shukuri, S. ; Ohba, A. ; Kouro, Y. ; Sakamoto, O. ; Fukumoto, A. ; Nakajima, M.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

124

Lastpage

125

Abstract

A 3.3 V single-supply 32 Mb flash memory realizing a 512B per sector program/erase unit features serial sector read, sector program and sector erase modes. By using AND cells and connecting one sense and latch (SL) circuit to every data line (DL) pair, these modes can handle data strictly sector by sector (512B). The same sector size for both programming and erasing simplifies the rewrite operation to a small number of sectors and prevents system performance degradation. The chip is implemented in a 0.45 /spl mu/m triple-well CMOS process.

Keywords

CMOS memory circuits; 0.45 micron; 3.3 V; 32 Mbit; AND flash memory; high-density memory chip; sector erase mode; sector program mode; serial sector read mode; single-supply operation; triple-well CMOS process; Circuits; EPROM; Flash memory; Latches; Least squares approximation; Sea measurements; Semiconductor device measurement; Space vector pulse width modulation; Switches; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535458

Filename

535458