The effect of logic block complexity on area of programmable gate arrays

The authors explore the tradeoff between the area of a programmable gate array (PGA) and the functionality of its logic block. A set of industrial circuits is implemented as PGAs using tools for technology mapping, placement, and routing. A simple model allows the exploration of a range of programming technologies and accounts for the area required by wiring. Experiments indicate that for combinational logic blocks implemented using lookup tables, the best number of inputs to use is between three and four, and that a D flip-flop should always be included in the logic block. These results are independent of the programming technology