Fully IEEE1149.1 compatible DFT solution for MIPS CPU CORE

This article presents a DFT (design-for-test) solution which uses hardware and software cooperation to realize MIPS CPU CORE DFT. The hardware is fully compatible with IEEE1149.1 standard test access port and boundary-scan architecture (2001) (JTAG), supporting breakpoint, step, internal key register watch function and can be extended. Software uses GUI programming to achieve visual DEBUG. The design in this paper is meaningful for reducing the test costs for CPU design, increasing design efficiency and accumulating experience of DFT strategy for CPU test. It assumes reader familiarity with IEEE1149.1.