On measuring the transparentability of cores in core-based ICs

Core-based IC design introduces more test challenges, especially in an open design environment. Macro test is an effective test strategy. However, the measurement of plenitude of transfers and effects which crucially affects the test protocol expansion remains a problem, and the high-level abstraction of description of cores contributes to this measurement difficulty. In this paper, transparentability is defined to represent the ability that a core can be treated as transparent to the core-under-test in test phase. Then some measuring factors of it independent of circuit structure are proposed. They are further classified into transparentability level 1 and level 2. The two levels of transparentability may be used as a common measurement, even if the core is described in RT level or higher abstraction level, and they are not limited to be used in macro test. The differences between transparentability and conventional testability are also discussed.