SLIM: third generation of packaging beyond MCM, CSP, flipchip and micro-via board technologies

The Packaging Research Center at Georgia Tech proposes to address packaging needs by using a technical vision for the next generation of packaging similar to what ICs did for transistors over the last four decades: continued integration to ever higher transistor density while maintaining manufacturing cost. This technical vision for the next generation of packaging looks at the current industry standard of a QFP wire bonded to the IC on a surface mount board; ceramic discretes are also surface mounted. For applications such as cellular phones, camcorders, or magnetic disk drives, the packaging efficiency, defined as the ratio of the area of all silicon and other ICs to the area of system-level board, is about 7% with this technology. The technical vision of integration of all of these packaging levels into one level with dielectrics, conductors, capacitors, resistors, inductors, and optoelectronics (as waveguides) is proposed to raise this efficiency to about 80%. This is primarily for two reasons: (1) discretes are now embedded into the substrate and thus take up no additional substrate surface area, and (2) all of the integration and extensive thin film wiring allows ICs to be flip-chip bonded “wall-to-wall” on the substrate. This integrated module can be a single chip, chip-scale module in the short-term, referred to as SCIM (single chip integrated module), the size of which is no bigger than the IC itself with as much as 5000 I/Os, or an integrated multichip module referred to as IMCM or single level integrated module board (SLIM)