Title :
A 15 ns 2500 gate highly flexible CHMOS EPLD
Author :
Swartz, Ronald W. ; Allen, Michael J.
Abstract :
A 2500-gate, 15-ns CMOS electrically programmable logic device (EPLD) with configurable inputs, expandable sum of products (SOP), and SOP implementation of control signals has been developed. Independent synchronous or asynchronous clocking of the inputs and outputs, plus both internal and pad feedback of each macrocell, makes this an extremely configurable 40-pin logic device. A combination of high speed, high density, and flexible architecture makes this device an ideal solution for high-speed microcomputer system design
Keywords :
CMOS integrated circuits; cellular arrays; large scale integration; logic arrays; 15 ns; CHMOS EPLD; CMOS PLD; LSI; SOP implementation; asynchronous clocking; configurable 40-pin logic device; configurable inputs; control signals; electrically programmable logic device; expandable sum of products; flexible architecture; high density; high speed; independent synchronous clocking; macrocell; pad feedback;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56696
