DocumentCode :
2687764
Title :
An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique
Author :
Chern, J.-G. ; Abidi, A.A.
fYear :
1989
fDate :
15-18 May 1989
Abstract :
An 11-bit, audio-speed analog-to-digital (A/D) converter for echo cancellation applications, which appears to consume the smallest chip area of any comparable converter, has been developed. It digitizes an analog input using the multislope integration technique, and requires one external capacitor. The DC and dynamic performance of the A/D converter were measured. The measured error plot indicates an integral nonlinearity of ±2 LSB (least significant bit) at 12 bits with no missing codes. A differential nonlinearity of ±0.5 LSB at 12 bits was measured using a statistical method. An S/N (signal-to-noise) versus input level measurement, obtained from the spectrum of the digitized output, indicates the effective dynamic linearity of the converter to be between 10 and 11 bits. The bandwidth is set by the sample-and-hold circuit
Keywords :
CMOS integrated circuits; analogue-digital conversion; 11 bit; A/D converter cell; CMOS; DC performance; SNR measurement; audio speed ADC; chip area; dynamic performance; input level measurement; multislope integration technique; statistical method;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
Type :
conf
DOI :
10.1109/CICC.1989.56698
Filename :
5726167
Link To Document :
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