New era for high performance and low cost semiconductor packaging

Summary form only given. We cannot consider the future of packaging without the requirements for IC innovation. These requirements are described extensively in the SIA roadmap, including the number of I/O terminals, chip clock frequencies, off-chip frequencies, etc. Although operating voltages will be <2 V, chip heat dissipation will be greatly increased due to greater density and clock frequencies. However, junction temperature remains constant at 125°C. As semiconductor performance is better at lower temperatures, high performance applications use lower operating temperatures than stated values, which implies that the package is not required to be heat resistant beyond that temperature and that a significant margin exists for cost reduction in the packaging area. Due to performance and size/weight requirements, the chip will be flip chip bonded with a multichip bare chip attach structure. Using an encapsulated flip chip joint, lowering joint stress, enables flexible selection of both joint and carrier materials. Epoxy-based carriers will be used due to cost, even in high performance applications, as their reliability is sufficient for most applications. However, standardization of test methods is inevitable to use such low cost carriers effectively. As technology elements for a bare chip package are already available, a common understanding of chip shipping quality is the last infrastructure barrier to be overcome. Drastic innovation is expected to simplify the chip bonding process. “Instant chip attach” technologies will emerge for low cost/high volume production