Title :
A 10-bit high speed CMOS CAS macrocell
Author :
Vogt, Alexander W. ; Dedic, Ian J.
Abstract :
A 10-bit 50 M-sample/s digital-to-analog converter has been fabricated in a 3-μm, double-metal, single-polysilicon CMOS process. The architecture of the converter was chosen to minimize the effects of chip gradients, mismatches and transistor parameters, voltage drops in supply tracks, and other nonideal effects. Close attention was paid to the dynamic behavior of the converter to reduce output glitches and code-dependent distortion
Keywords :
CMOS integrated circuits; cellular arrays; digital-analogue conversion; 3 micron; chip gradients; code-dependent distortion; double-metal; dynamic behavior; high speed CMOS CAS macrocell; mismatches; nonideal effects; output glitches; single-polysilicon CMOS process; supply tracks; transistor parameters; voltage drops;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56703
