Title :
A differential PLL architecture for high speed data recovery
Author :
Co, Ramón S. ; Liang, Jui C. ; Ouyang, Kenneth W.
Abstract :
A differential phase-locked-loop architecture that can be used in high-speed data recovery systems is described. The differential architecture has superior tracking performance in the presence of noise and thus superior bit-error-rate performance compared to the conventional single-ended realization. For operation at 10 Mb/s using a Manchester line code, the theoretical limit of ±25-ns jitter margin has been approached. The device, which is fabricated in a 1.25-μm digital CMOS process, includes zero-phase start circuitry for instant phase/frequency acquisition, a precision self-calibrated delay element, and a line receiver/driver for a complete line interface function
Keywords :
CMOS integrated circuits; digital integrated circuits; phase-locked loops; 1.25 micron; 10 Mbit/s; Manchester line code; bit-error-rate performance; differential PLL architecture; digital CMOS process; high speed data recovery; instant phase/frequency acquisition; jitter margin; line interface function; line receiver/driver; precision self-calibrated delay element; tracking performance; zero-phase start circuitry;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56705
