A differential PLL architecture for high speed data recovery

A differential phase-locked-loop architecture that can be used in high-speed data recovery systems is described. The differential architecture has superior tracking performance in the presence of noise and thus superior bit-error-rate performance compared to the conventional single-ended realization. For operation at 10 Mb/s using a Manchester line code, the theoretical limit of ±25-ns jitter margin has been approached. The device, which is fabricated in a 1.25-μm digital CMOS process, includes zero-phase start circuitry for instant phase/frequency acquisition, a precision self-calibrated delay element, and a line receiver/driver for a complete line interface function