Title :
A DFT and test pattern generation methodology for an ARM powered® SoC design
Author :
Li Rui ; Ling Ming ; Xie Yongming ; Ren Ailing
Author_Institution :
Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China
Abstract :
This paper describes the design-for-testability (DFT) methodology for an ARM powered SoC (system-on-a-chip) design which is named by Garfield and used for hand-held computing. Various test methods, including scan insertion, memory BIST (built-in self-test), boundary scan and functional test, and the strategies merging the above methods in SoC design are discussed in detail.
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; design for testability; integrated circuit design; integrated circuit testing; system-on-chip; DFT; SoC design; boundary scan; design-for-testability methodology; functional test; hand-held computing; memory BIST; scan insertion; system-on-a-chip design; test methods; test pattern generation methodology;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277426
