Low power circuits and microarchitectures for gigascale integration

Technology scaling continues providing integration capacity of billions of transistor; however, power delivery and dissipation are the barriers. Supply voltage scaling - which provides relief in active power reduction - has to slow down to limit subthreshold leakage. A variation in process, temperature, and supply voltage forces a major change in the design paradigm, from deterministic to probabilistic design. Therefore, business as usual is not an option. In this paper we address leakage problem and provide various leakage reduction techniques, which include a dynamic sleep transistor and a dynamic body bias technique. In addition, we discuss advances in circuits and microarchitectures to exploit future gigascale integration capacity for a system on a chip (SOC) by an experimental 10Gbps Ethernet TCP/IP processor, to help integrate diverse functional blocks, providing valued performance, with better power efficiency and design productivity.