Title :
Physical implementation and test of energy recovery circuit
Author :
Zhang Sheng ; Zhou Runde
Abstract :
This paper presents a new structure of energy recovery logic named improved energy recovery logic (IERL) and discusses the physical implementation issues. A feasible test schemes for function verification and power measurement of energy recovery logic circuit is proposed and put in practice. The test results verified the proper function of IERL 2-bit full adder (FA) circuit and the low power performance. When the power clock is set at 2MHz, the average power consumption of IERL 2-bit FA is 66% of its CMOS counterpart.
Keywords :
adders; logic circuits; logic testing; low-power electronics; power measurement; 2 MHz; CMOS; IERL; energy recovery circuit; feasible test schemes; full adder circuit; function verification; improved energy recovery logic; low power performance; physical implementation; power clock; power measurement;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277430
