Design of low power buffer using driver-array for on-chip IPs interconnection

A novel design method of low power buffer is presented. The design flow uses driver-array to optimize the equivalent multi-stage buffer and inserts an additional inverter to keep the same fan-out of the logic signal. It avoids the sightless determination when design interconnection buffers and achieves 4.96%, 42.15% and 22.30% savings of delay, area and power consumption, respectively.